DARPA making it easier to develop custom, secure chips
Defense Advanced Projects and Research Agency aims to dramatically shorten the process and reduce costs for producing more secure advanced chips.
To make it easier for the military to run advanced applications on its systems, the Defense Advanced Projects and Research Agency announced it is supporting U.S.-based manufacturing initiative that can improve the delivery of custom chips for defense systems.
Under the Structured Array Hardware for Automatically Realized Applications (SAHARA) program, DARPA will work with Intel and researchers from University of Florida, University of Maryland and Texas A&M, to automate and scale the conversion of defense-relevant field-programmable gate array (FPGAs) designs into quantifiably more secure structured application-specific integrated circuits (ASICs).
ASICs are custom chips designed to maximize the efficiency of a specific algorithm. These chips can deliver higher performance and lower power consumption for defense electronic systems, but they can take years to develop and cost hundreds of millions of dollars, according to DARPA. Most applications run on general purpose FPGAs, which are far less efficient. Currently, converting FPGAs to structured ASICs is not only complex and costly, but also fails to address design security considerations. SAHARA aims to solve both issues.
Intel already produces “eASIC” devices, structured ASICs that are an intermediary technology between FPGAs and standard-cell ASICs. They offer a lower unit cost and run on less power than FPGAs. Additionally, they cost less to engineer and provide a faster time to market than standard-cell ASICs, Intel said in its announcement. Intel and its partners plan to automate the conversion process for both currently fielded and future FPGAs.
The conversion will dramatically shorten the design process, reduce associated engineering costs and enhance chip security, DARPA officials said. Additionally, Intel aims to build U.S.-based manufacturing capabilities for the structured ASICs -- something not currently available.
The research teams are also working on new chip protections that leverage verification and validation and can address supply chain threats by thwarting reverse engineering and counterfeiting attacks. Once proven, the countermeasures will be integrated into Intel’s structured ASIC design flow.
“SAHARA aims to enable a 60% reduction in design time, a 10X reduction in engineering costs, and a 50% reduction in power consumption by automating the FPGA-to-Structured ASICs conversion,” said Serge Leef, a program manager in DARPA’s Microsystems Technology Office. “The partnership with Intel will ultimately afford the DOD with significant cost and resource savings while enabling the use of leading-edge microelectronics across a host of applications.”
This article first appeared on GCN, a Defense Systems partner site.